1. Field of the Invention
The present invention relates to an input circuit, more particularly, the present invention relates to a high voltage tolerant input circuit capable of operating at extremely low input/output (IO) supply voltage.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a conventional high voltage tolerant input circuit 100. Referring to FIG. 1, the conventional input circuit 100 includes a diode D1, a resistor R1, an NMOS transistor NM1 and a buffer G1. In general, the diode D1 is an electrostatic discharge (ESD) protection device. The resistor R1 is used for protecting the NMOS transistor NM1 and the buffer G1 by adding a delay and reducing the noise level of the external input voltage VIN. A gate terminal of the NMOS transistor NM1 would be biased on an input/output (IO) supply voltage VDDIO, so that the NMOS transistor NM1 would receive the external input voltage VIN and output the internal input voltage VINN to the buffer G1.
However, the highest voltage level of the internal input voltage VINN would be restricted by the NMOS transistor NM1 at VDDIO-VthN, where VthN is the threshold voltage of the NMOS transistor NM1. Accordingly, even higher voltage level of the external input voltage VIN (for example, VDDIO) can not be supplied to the buffer G1 directly. Moreover, the conventional input circuit 100 does not operate at very low IO supply voltage VDDIO. To be specific, if the IO supply voltage VDDIO is very low, the internal input voltage VINN can not reach the threshold voltage of the buffer G1.